1. Field of the Invention
The present invention relates to a semiconductor memory which requires fresh operations to retain data written in its memory cells.
2. Description of the Related Art
Hand-held terminals such as cellular phones are growing in memory capacity requirement year by year. Under the circumstances, dynamic RAMs (hereinafter, referred to as DRAMs) have come to be used as the work memories of the cellular phones instead of conventional static RAMs (hereinafter, referred to as SRAMs). DRAMs are smaller than SRAMs in the numbers of devices that constitute the memory cells. DRAMs can thus be reduced in chip size, with lower chip cost than that of SRAMs.
Meanwhile, semiconductor memories to be mounted on cellular phones must be low in power consumption so as to allow prolonged use of the batteries. Unlike SRAMs, DRAMs require periodic refresh operations in order to retain data written in their memory cells. Consequently, when DRAMs are used as the work memories of cellular phones, data retention alone can consume power to exhaust the batteries even if the cellular phones are not in use.
In order to reduce the power consumption of the DRAMs during standby (in low power consumption mode), there have been developed partial refresh technology and twin cell technology.
According to the partial refresh technology; the number of memory cells to be refreshed is reduced by limiting the number of memory cells to retain data in a standby state. Reducing the memory cells to refresh can decrease the number of times of refresh, with a reduction in the power consumption during standby.
According to the twin cell technology, complementary data is stored into two memory cells (memory cell pair) which are connected to complementary bit lines, respectively. This doubles the charges retained in the memory cell pair. Since the two memory cells retain “H” data and “L” data, respectively, the refresh interval is determined by a longer one between the data retention times of “H” data and “L” data. That is, the worst data retention time is the sum of the characteristics of the two memory cells, not the characteristic of one single memory cell. On the contrary, in a single memory cell, the refresh interval is determined by a shorter one between the data retention times of “H” data and “L” data. As above, according to the twin cell technology, retaining data in two memory cells makes it possible to compensate a small leak path, if any, in one of the memory cells with the other memory cell.
In the partial refresh technology described above, to reduce the power consumption during the low power consumption mode requires that the data retention areas be small. As a result, the lower the power consumption, the smaller the memory capacity available for retention during the low power consumption mode.
In the twin cell technology, two memory cells are always used to retain a single bit of data not only in refresh operations but also in normal read operations and write operations. Storing a single bit hence requires a memory cell size twice as big as that of a single memory cell, which results in increasing chip cost. Consequently, in the cases of DRAMs to which the twin cell technology is applied, there is not much advantage in replacing the SRAMs mounted on cellular phones with the DRAMs.